1. Field of the Invention
The present invention relates to an MOS gate array device and, more particularly, to an MOS gate array device having a special area for forming a memory.
2. Description of the Prior Art
The function of MOS gate arrays has been diversified in recent years and an MOS gate array having a special area for forming a memory, namely, a storage area, in addition to a logic area has been developed.
In an MOS gate array, a plurality of MOS transistor areas are formed in a regular arrangement on the surface of a silicon substrate so that a memory IC can be formed readily by only wiring metal lines. The logic area has MOS transistor areas and wiring areas which are so arranged that various logic ICs can readily be formed by only wiring metal lines on the surface of the silicon substrate.
When a memory, for example, a RAM, having a small storage capacity is formed in the storage area of the conventional MOS gate array, most portions of the storage area becomes useless deteriorating plane availability. Attempts have been made to form a logic IC in the unused additional storage area.
Generally, it is impossible to form a logic IC in the storage area because the logic IC requires complicated metal wiring. Forming a memory IC in the logic area is desadvantageous because the degree of circuit integration is deteriorated.
However, it is comparatively easy to form a PLA (programmable logic array) circuit as a logic circuit having an AND array plane and an OR array plane in the storage area by wiring metal lines.
Japanese Patent Laid-Open Publication No. 59-225615 discloses a technique to constitute a PLA circuit by suitably connecting elements formed in a RAM forming area.
According to the prior art, a plurality of basic unit circuits areas 4 each comprising, for example, six MOS transistors P1, P2, N1, N2, N3 and N4 in a memory area of a gate array as shown in FIG. 7(a) are formed previously in a regular arrangement.
As shown in FIG. 7(b), the basic unit circuit 4 constituting a 6-transistor memory cell of a SRAM IC is formed by forming bit lines 10 and 11, a word line 12 and a ground line by using metal layers.
As shown in FIG. 6, the SRAM IC includes an address decoder area 1, a storage element matrix area 2 and a data control area 3. The storage element matrix area 2 can be formed by efficiently using the storage space by connecting the respective bit lines 10 and 11, and word lines 12 of the plurality of basic unit circuits 4 by wiring metal lines.
However, in forming a PLA circuit by the basic unit circuits in the storage area of a MOS gate array, the basic unit circuits 4a and 4b are formed in the same metal wiring pattern as shown in FIG. 8. Therefore, a wiring 26 along a roundabout route is necessary for connecting the output 10a of the basic unit circuit 4a with the input 12b of the basic unit circuit 4b.
Furthermore, in a PLA circuit shown in FIG. 9, an AND array plaane comprises an input circuit 20 and a first NOR plane 21, while an OR array plane comprises pull-up circuits 23 and 24, an output circuit 25 and a second NOR plane 22.
As shown in FIG. 8, a wiring metal line 26 extending along a roundabout route is necessary for connecting the output of the AND array with the input of the OR array plane.
As evident from the foregoing description, the conventional PLA using the RAM space of the MOS gate array cannot be formed in a compact construction eliminating space for wiring.